CS 315 Computer Security: Fengwei Zhang

CSE 5030 Advanced Computer Architecture

Spring 2026 -- Fengwei Zhang

Instructor: Fengwei Zhang
Class Time: Tuseday 10:20AM - 12:10AM
Class Location: Room 302, Teaching Building III Zhihua
Lab Time: Monday, 02:00PM - 03:50PM
Lab Location: Room 504, Teaching Building III Zhihua

Syllabus: [PDF]
Office Address: Engineering Building, South Tower, Room 515
Homepage: http://cse.sustech.edu.cn/faculty/~zhangfw
Email: zhangfw (at) sustech (dot) edu (dot) cn

Course Objectives

This course offers an in depth experience of real-world threats and defenses. Upon successful completion of this class, the student will gain experience in:

Understand the fundamental principles, performance evaluation methods, and design trade-offs in modern computer architecture
Analyze the RISC-V ISA and the XiangShan microarchitecture
Develop the ability to read and understand top-tier architecture conference papers (e.g., ISCA, MICRO, HPCA, ASPLOS)
Design, simulate, or optimize a high-performance processor or accelerator module through hands-on projects
Understand emerging trends in architecture, including system security and AI acceleration

Teaching Methods

Lectures + Paper Reading & Presentation (top-tier papers) + Lab;
XiangShan open-source architecture lab: simulate microarchitectural components (e.g., cache, predictor, fetch unit) using RISC-V simulators and tools like GEM5;
Paper Reading & Presentation: Students work in groups to complete a microarchitecture design or optimization project, submit a technical report, and give a presentation.

Prerequisites

CS202 Principles of Computer Organization
CS302 Operating Systems

Recommended Book

John L. Hennessy & David A. Patterson, Computer Architecture: A Quantitative Approach, 6th Edition, 2019.

Grading Policy

The grades for the course will be based upon the tables given below

Topics	Grade
Class Participation	100
Paper Reading & Presentation	200
12 intensive Lab Assignments	600
Final Exam	100
Total	1000

Gradding Scale

A+	97 - 100%	C+	77 - 79%
A	93 - 96%	C	73 - 76%
A-	90 - 92%	C-	70 - 72%
B+	87 - 89%	D+	67 - 69%
B	83 - 86%	D	63 - 66%
B-	80 - 82%	D-	60 - 62%
F	0 - 59%

Academic Dishonesty

More details on Regulations.

Student Disabilities Services

If you have a documented disability that requires accommodations, you will need to register with the University for coordination of your academic accommodations, or let me know.

Class Schedule

Date	Topic	Reading & Notes (tentative)	Slides & Labs
Week 01, 03/03	Course Introduction & Architecture Evaluation		[Slides and Lab]
Week 02, 03/10	Instruction-Set Architecture (ISA)	Lab 1 Due	[Slides and Lab]
Week 03, 03/17	Caches & Memory Management	Lab 2 Due	[Slides and Lab]
Week 04, 03/24	Pipelining	Lab 3 Due	[Slides and Lab]
Week 05, 03/31	Advanced Pipelines	Lab 4 Due	[Slides and Lab]
Week 06, 04/07	Branch Prediction	Lab 5 Due	[Slides and Lab]
Week 07, 04/14	Cache Coherence	Lab 6 Due	[Slides and Lab]
Week 08, 04/21	Memory Consistency	Lab 7 Due	[Slides and Lab]
Week 09, 04/28	Xiang-Shan Micro-Architecture	Lab 8 Due	[Slides and Lab]
Week 10, 05/05	Labor Day	No CLASS
Week 11, 05/12	Vector ISA	Labs 9 Due	[Slides and Lab]
Week 12, 05/19	Parallel & Heterogeneous Computing	Labs 10 Due	[Slides and Lab]
Week 13, 05/26	Secure Architectures	Lab 11 Due	[Slides and Lab]
Week 14, 06/02	Research Paper Reading & Presentation	Lab 12 Due	[ Slides]